Owing to the progress of semiconductor packaging technology and improvements in electrical performances for semiconductor chips, semiconductor devices are developed toward high integration. For example, a ball grid array (BGA) semiconductor device is characterized in that a plurality of array-arranged solder balls are formed on a bottom surface of a substrate and used as input/output (I/O) connections for electrically connecting a semiconductor chip mounted on the substrate to an external device such as printed circuit board (PCB). Compared to a conventional lead-frame based semiconductor device, the BGA semiconductor device advantageously provides more I/O connections on the same unit area of a chip carrier such as the substrate, and thus can accommodate more electronic circuits and semiconductor chips therein.
In accordance with high integration of the semiconductor device, more leads or contacts are required and also more noise is caused. Generally, for solving the noise problem, passive components such as resistors, capacitors and inductors are incorporated in the semiconductor device so as to eliminate the noise and stabilize the circuits, making a semiconductor chip packaged in the device have specific current characteristics.
FIG. 1 is a cross-sectional view showing a conventional passive component being mounted on a surface of a substrate. At least one pair of separate bond pads 11 are formed at predetermined positions on the surface of the substrate 10 and are exposed to a solder mask layer 12 that covers the substrate 10. Then, a solder paste 13 is applied on the bond pads 11, and two ends 140 of at least one passive component 14 are respectively attached to the bond pads 11 via the solder paste 13. A reflow process is performed to allow the passive component 14 to be bonded and electrically connected to the bond pads 11 on the substrate 10 via the solder paste 13. However, it is difficult to accurately control an applied amount of the solder paste 13, and the height of the solder paste 13 after being reflowed, as well as the surface flatness of the solder mask layer 12. Thereby, a gap 15 is usually left between the passive component 14 and the solder mask layer 12. In a high-temperature environment during subsequent fabrication processes, the solder paste 13 would melt or become softened and leaks to the gap 15 due to capillary attraction, which causes bridging of the solder paste 13 applied on the two bond pads 11 and short-circuiting of the passive components 14, and thus adversely affects the production yield.
Referring to FIG. 2 disclosed in U.S. Pat. No. 6,108,212, a bond pad 21 and at least one electrode 22 are formed on a surface of a substrate 20, and an electrically resistive volume 23 is disposed between the bond pad 21 and the electrode 22 to form a passive component comprising the bond pad 21, the electrode 22 and the electrically resistive volume 23. This allows the substrate 20 to be electrically connected to an external electronic device 25 such as printed circuit board by means of a metal bump 24 bonded to the bond pad 21. Also, the passive component formed by the bond pad 21, the electrode 22 and the electrically resistive volume 23 provides improved electrical performances for the semiconductor device. A pitch distance between the bond pad and the electrode on the surface of the substrate should be sufficiently large for successfully forming the electrically resistive volume having resistor effects. However, since the substrate has a limited surface area, a relatively large area occupied by the resistor would affect a layout of other circuits arranged on the substrate surface. This thus reduces flexibility of circuit routability on the substrate, sets a limitation on the number of passive components that can be incorporated on the substrate, and does not facilitate the high integration development for the semiconductor device. Furthermore, by the fact that the number of passive components to be incorporated is dramatically increased along with the requirement of high performances for the semiconductor device, if the foregoing method in which a semiconductor chip and a large number of passive components are simultaneously mounted on the substrate surface is employed, the size miniaturization for the semiconductor device can hardly be achieved.
In order to solve the above problem, U.S. Pat. No. 6,278,356 discloses a substrate 30 having a built-in layer passive component. Referring to FIG. 3, a copper layer 32 is formed respectively on an upper surface and a lower surface of an insulating layer 31, and the copper layer 32 is provided with an etching pattern 320. Then, a dielectric layer 33 is printed on the copper layer 32 and fills openings in the etching pattern 320. Subsequently, a resistive layer 34 is formed over the copper layer 32 and the dielectric layer 33 by the printing technique, wherein the resistive layer 34 serves as a resistor, and the dielectric layer 33 filling the openings in the etching patter 320 serves as a capacitor, so as to integrate a plurality of passive components on the substrate 30.
However, in the foregoing structure, only the printing technique is used to form the dielectric layer 33 and the resistive layer 34 on the substrate 30, such that it is difficult to accurately control the capacitance and resistance thereof respectively. Additionally, since the resistive layer 34 covers both the copper layer 32 and the dielectric layer 33 that are made of different materials, a reliability issue may be generated in a high-temperature and high-moisture environment during subsequent fabricating processes or tests, and thus electrical connection between the resistive layer and electrodes may also be affected.
Moreover, along with the blooming development of electronic industry, electronic products are gradually becoming more multi-functional and high efficient. In order to satisfy the requirements of high integration and size miniaturization for semiconductor packages, a circuit board for carrying active/passive components and circuits has been developed from a single-layer structure to a multi-layer board that employs the interlayer connection technique to enlarge usable circuit area on the circuit board, so as to incorporate a high circuit density in the circuit board. However, the foregoing prior art only discloses that passive components can be mounted on the surface of the substrate but does not provide a strategy to apply passive components to a multi-layer package substrate in accordance with the requirements of high integration and size miniaturization for the semiconductor package.
Therefore, the problem to be solved here is to incorporate an effective number of electronic elements such as passive components and semiconductor chips in a semiconductor package substrate with multiple layers of circuits, which can assure the fabrication reliability and accuracy and improve electrical performance of electronic products, without affecting circuit routability of the substrate and increasing the overall thickness of the semiconductor package, so as to meet the requirements of compact size, multiple functions and high electrical performances of the electronic products.